Not Applicable
In the production of semiconductor integrated circuits and other semiconductor articles from semiconductor wafers, it is often necessary to provide multiple metal layers on the wafer to serve as interconnect metallization which electrically connects the various devices on the integrated circuit to one another. Traditionally, aluminum has been used for such interconnects, however, it is now recognized that copper metallization may be preferable.
The application of copper onto semiconductor wafers has; in particular, proven to be a great technical challenge. At this time copper metallization has not achieved commercial reality due to practical problems of forming copper layers on semiconductor devices in a reliable and cost efficient manner. This is caused, in part, by the relative difficulty in performing reactive ion etching or other selective removal of copper at reasonable production temperatures. The selective removal of copper is desirable to form patterned layers and provide electrically conductive interconnects between adjacent layers of the wafer or other wafer.
Because reactive ion etching cannot be efficiently used, the industry has sought to overcome the problem of forming patterned layers of copper by using a damascene electroplating process where holes, more commonly called vias, trenches and other recesses are used in which the pattern of copper is desired. In the damascene process, the wafer is first provided with a metallic seed layer which is used to conduct electrical current during a subsequent metal electroplating step. The seed layer is a very thin layer of metal which can be applied using one or more of several processes. For example, the seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer on the order of 1000 angstroms thick. The seed layer can advantageously be formed of copper, gold, nickel, palladium, and most or all other metals. The seed layer is formed over a surface which is convoluted by the presence of the vias, trenches, or other device features which are recessed. This convoluted nature of the exposed surface provides increased difficulties in forming the seed layer in a uniform manner. Nonuniformities in the seed layer can result in variations in the electrical current passing from the exposed surface of the wafer during the subsequent electroplating process. This in turn can lead to nonuniformities in the copper layer which is subsequently electroplated onto the seed layer. Such nonuniformities can cause deformities and failures in the resulting semiconductor device being formed.
In damascene processes, the copper layer that is electroplated onto the seed layer is in the form of a blanket layer. The blanket layer is plated to an extent which forms an overlying layer, with the goal of completely providing a copper layer that fills the trenches and vias and extends a certain amount above these features. Such a blanket layer will typically be formed in thicknesses on the order of 10,000-15,000 angstroms (1-1.5 microns).
The damascene processes also involve the removal of excess metal material present outside of the vias, trenches or other recesses. The metal is removed to provide a resulting patterned metal layer in the semiconductor integrated circuit being formed. The excess plated material can be removed, for example, using chemical mechanical planarization. Chemical mechanical planarization is a processing step which uses the combined action of a chemical removal agent and an abrasive which grind and polish the exposed metal surface to remove undesired parts of the metal layer applied in the electroplating step.
Automation of the copper electroplating process has been elusive, and there is a need in the art for improved semiconductor plating systems which can produce copper layers upon semiconductor articles which are uniform and can be produced in an efficient and cost-effective manner. More particularly, there is a substantial need to provide a copper plating system that is effectively and reliably automated.
A lift/tilt assembly for use in a semiconductor wafer processing device is set forth. The lift/tilt assembly includes a linear guide comprising a fixed frame and a moveable frame. A nest for accepting a plurality of semiconductor wafers is rotatably connected to the moveable frame. The nest rotates between a wafer-horizontal orientation and a wafer-vertical orientation as it is driven with the movable frame by a motor that is coupled to the linear guide. A lever connected to the nest provides an offset from true vertical for the nest when the nest is in the wafer-vertical orientation.